Implementing monolithic voltage controlled oscillators (VCOs) in standard complementary metal oxide semiconductor (CMOS) technology is a major challenge for the design of radio-frequency (RF) CMOS transceiver integrated circuits (ICs). Recent work has shown that MOS devices for voltage control can produce better VCO performance than commonly used diode varactors. These advantages include better tuning range, better Q, and so better VCO phase noise. Both nMOS and pMOS variety devices can be used as varactors, typically with source and drain terminals shorted (S=D), and a tuning voltage applied to the gate terminal with respect to the source and drain.
Several modes of MOS varactor operation are known depending on the connection of the fourth device terminal, the transistor back gate (BG). For standard bulk p-type substrate CMOS technology, only pMOS devices can be used since the back gate BG of nMOS devices are tied to a grounded substrate. New triple well CMOS technologies, now common in 0.18 and 0.13 μm gate lengths, offer a triple well option that extends the flexibility of BG terminal connection for an nMOS device. nMOS devices have advantages over pMOS devices as varactors in terms of better Q and better capacitance range.
When used in a VCO, MOS varactors typically operate under large signal tank swings necessary for good phase noise and moderate gain constant (Kvco) or tuning gain (Hz/V). These large signals, typically 1 to 8 volts peak-to-peak over a back to back, series connected, pair of varactors, are well known to linearize the sharp capacitance variation with a tuning voltage (C(V)) which typically varies from Cmin to Cmax in a few hundred mV under small signal conditions.
Three MOS varactor modes of operation are recognized. In the first mode (Mode 1), the pMOS BG is tied to the drain supply voltage VDD, or the nMOS substrate is grounded, or a triple well nMOS BG is tied to ground. This mode (S=D, BG=GND as nMOS) has superior C(V) range, using the inversion MOS bias region of operation only. For this reason, it is called I-MOS for inversion MOS. One disadvantage of this mode with supply referenced VCO tanks and/or tuning voltages is a sensitivity to supply noise and supply variations (frequency pushing). This deficiency often requires a remedy of additional supply regulation and/or large off-chip capacitor filtering that are undesirable for low power and low cost communication applications.
The second MOS varactor mode (Mode 2) ties the pMOS or triple well nMOS back gate BG to the source and drain. This mode (S=D=BG) has a reduced C(V) range, and uses both inversion and accumulation MOS bias regions of operation. It is not sensitive to supply noise or frequency pushing because its BG is isolated from both supply and ground. But, under typical large signal VCO swing operation it has less than half the tuning range, which makes it less advantageous to use.
Standard CMOS technologies have process and temperature variations that must be tuned out by the VCO. Also, many communication applications (such as Sonet OC-192) have multiple rates or frequencies that must be tuned to (9.954, 10.66, 11.1 GHz for OC-192). Both requirements make a large VCO tuning range or large varactor C(V) range important. Even for implementations that use other methods for tuning to rate or tuning out process variations (for example, multiple switched VCOs and discreet tuning methods such as switched capacitors or inductors), frequency variations from temperature effects alone still make a large varactor C(V) range important because these alternative tuning methods present their own capacitance load to the VCO tank, there by decoupling or attenuating the C(V) effect of the varactor alone.
The third MOS varactor mode (Mode 3) is an accumulation-only device called an A-MOS device. It is formed by removing source and drain diffusions (p+ type for a pMOS device), and perhaps adding bulk contacts (n+ type for what was a pMOS device). The resulting device has a floating BG and is not strictly a MOS transistor device. The A-MOS floating BG makes it insensitive to supply noise/pushing in a VCO application. While the A-MOS C(V) range is typically as large as an I-MOS even under large signal operation, it suffers from the disadvantage of not being a commonly used, well-modeled CMOS device structure such as the standard nMOS or pMOS devices. As a result, the A-MOS device often is not well-controlled, reliably fabricated, or accurately modeled.